A Functional Semantics for Delta Delay Vhdl Based on Focus

This tutorial paper gives a functional semantics for delta delay VHDL i e VHDL restricted to zero delay signal assignments In combination with the sequential state ments zero delay signal assignment is su cient to generate the full algorithmic ex pressibility of VHDL The restriction is useful for a formal semantics of VHDL aimed at higher levels of abstraction where real absolute and precise timing often is painful if not impossible to prescribe The approach employs the functional speci cation methodology Focus which is based on the concept of streams and stream processing functions It advocates a three level semantics re ecting VHDL s three syntactic levels of expressions statements and processes